Charge coupled devices (CCD's) have been used for several years as a basic signal processing element of computers and the like, and these devices typically include signal input and output electrodes disposed on the surface of a semconductor body for injecting and receiving charge, respectively, which is propagated along the "channel" of the CCD. This channel will typically be part of an epitaxial layer which has been previously grown on a larger underlying semiconductor substrate member. This epitaxial channel approach is used to provide appropriate purity and thickness control over the CCD channel, which is the main charge transfer medium of the structure. As is well known, a plurality of charge transfer electrodes are selectively spaced between these input and output CCD electrodes and are adapted to receive individually controllable "clock" signals. These clock signals are received in preestablished phase relationships for controlling the flow (direction, velocity and amplitude) of charges or charge packets which are propagated along the CCD channel between input and output electrodes.
The earliest CCD's were fabricated in silicon, rather than GaAs, partially as a result of the advanced state of the silicon MOS planar techology and the ability to form high quality silicon dioxide passivation layers on silicon surfaces. This feature is particularly desirable where the CCD charge transfer electrodes are deposited on top of a surface insulating (SiO.sub.2) layer to receive control potentials which are capacitively coupled through the SiO.sub.2 insulating layer to control the flow of charge in the CCD channel region. Although several different surface dielectrics have been proposed and used for GaAs, there is no surface dielectric in the GaAs technology which is comparable in its quality and passivation characteristics with silicon dioxide in the silicon technology. For this reason, the use of metal-semiconductor barrier (Schottky barrier) gates, in contrast to insulated gates used in silicon technology, have been employed in all known GaAs CCDs.
On the other hand, GaAs CCDs offer certain distinct advantages over silicon CCDs as a result of the higher carrier mobilities and thus higher achievable switching speeds in GaAs as contrasted to silicon. Thus, as a result of these certain obvious advantages that this III-V compound material offers over silicon in the fabrication of high speed charge coupled devices, substantial efforts have been made recently in the GaAs CCD technology directed toward improving GaAs CCD process yields and integrated circuit array and device operation.
One of the requirements to be considered when fabricating large CCD arrays on a single chip of GaAs is that of electrically isolating adjacent CCDs, one from another, and confining charge flow to the channels of the individual CCDs and also preventing electrical charges from adjacent devices from entering a CCD channel. One approach to this electrical isolation requirement is to mesa etch the CCD channel layer, which typically will be an epitaxial, diffused or ion implanted layer, in order to physically isolate individual CCD's within distinct mesa regions on the gallium arsenide chip. These mesa etch approaches have been described in the following two publications: (1) W. Kellner, H. Bierhenke and H. Kniepkamp, 1977 IEDM Technical Digest, paper 24.7., and (2) I. Deyhimy, J. S. Harris, R. C. Eden, D. D. Edwall, S. J. Anderson and L. O. Bubulac, Appl. Phys. Lett. 32, 383 (1978).
Another approach which uses a combination of a mesa geometry and a surrounding metal guard ring or barrier is described by A. J. Hughes, W. Eccleston, R. A. Stuart, International Conference of Technology and Application of CCD's, 1974, at pages 270-273. However, all of these prior art approaches which use mesa geometries and Schottky barrier electrodes in the fabrication of gallium arsenide CCD's have the disadvantage that the presence of the semiconductor mesas increases the difficulty of performing the required photolithography, since it is difficult to achieve high resolution lithography on non-planar surfaces. Additonally, layers of insulation and metal which must be formed over these non-planar mesa surfaces often suffer from fatigue and cracking because of the mechanical stress imparted to these overlying layers by edges of the mesas. Furthermore, at sufficiently high voltages, voltage breakdown can occur at the lower edges or base of the mesa at its intersection with the underlining semiconductor material. Thus, the desirability of forming a completely planar Schottky barrier CCD or CCD array in a gallium arsenide semiconductor is manifest.